Electronic systems, such as computer systems, often require nonvolatile storage of data. For example, it is desirable to retain certain binary coded data when a computer system is powered down. Magnetic hard disk systems have dominated nonvolatile data storage media for computers and related electronic systems due to the low cost and high capacity of available magnetic hard disk systems. Magnetic hard disk drives operate by storing binary coded data as polarities on a magnetic media which can be rewritten quickly and as often as desired. Magnetic hard disk drives are bulky, somewhat delicate, and require large power consumption and movable parts that pose potential reliability problems.
Flash memory systems provide a compact, rugged, and low power consumption integrated circuit alternative to magnetic hard disk systems for nonvolatile data storage. A flash memory system typically includes an electrically isolated (floating) gate transistor memory cell as an electrically erasable and programmable read only memory (EEPROM) nonvolatile data storage element. The flash memory system architecture differs from a conventional EEPROM architecture in that the memory cells in a flash memory system are arranged in blocks and can be erased a block at a time and programmed a bit at a time. For an example of operation of a flash memory system, see B. Dipert et al. "Flash Memory Goes Mainstream," IEEE Spectrum, Vol. 30, No. 10, pp. 48-52, October 1993.
The floating gate transistor is programmed by charge transport of electrons across a gate insulator onto the floating gate for storage. The floating gate transistor is erased removing the stored electrons from the floating gate and transporting these charges back across the gate insulator. The floating gate transistor is read by detecting a current, the conductance of which varies depending on whether or not electrons are stored on the floating gate.
One example of programming an n-channel floating gate field-effect transistor (FET) includes applying approximately +12 Volts between a select/control gate (control gate), which is capacitively coupled to the floating gate, and a source region of the FET. Approximately +6 Volts is applied between a drain region of the FET and the source region. Electrons are accelerated from the source region toward the drain region in a channel region formed between the source and drain regions. The electrons acquire kinetic energy, thereby freeing additional electrons that are accelerated toward the drain region. High energy "hot" electrons are attracted across the energy barrier of the gate insulator by the electric field resulting from the high voltage applied to the control gate. The electrons that accumulate on the floating gate raise a turn-on threshold voltage (v.sub.T) magnitude that inhibit current conductance between the drain and source regions when a read voltage is applied to the control gate during a read operation.
One example of erasing the n-channel floating gate FET includes applying approximately -10 Volts to the control gate, +5 Volts to the source region, and isolating (floating) the drain region of the FET. Electrons that were previously stored on the floating gate are removed from the floating gate by Fowler-Nordheim tunneling of the electrons across the underlying gate insulator. The V.sub.T magnitude is decreased toward its unprogrammed value, allowing current conduction between drain and source regions when a read voltage is applied to the control gate during a read operation.
The large negative erasing control gate voltage required by the floating gate must be selectively applied to the particular block of memory cells being erased. For example, a separate power supply circuit can be dedicated to each block of memory cells to provide the large negative erasing voltage to the particular block of memory cells being erased. Alternatively, a single power supply circuit can be used to provide a common negative erasing voltage for all the blocks of memory cells, and an n-channel FET switch can be provided for each block of memory cells to route the large negative erasing voltage to the particular block of memory cells being erased.
As is well known in the art, n-channel FETs are typically preferred as switches for conducting voltages that are more negative than a control (gate) voltage. An n-channel FET becomes increasingly conductive as the gate voltage increasingly exceeds the source voltage. By applying a positive voltage to the gate that exceeds the source voltage by at least the n-channel FET's V.sub.T magnitude, the n-channel FET easily passes the source voltage to a drain region of the n-channel FET.
One drawback of the n-channel FET is that a source-to-substrate pn junction diode turns on and injects minority charge carriers into the substrate when the voltage at the source becomes substantially more negative than a voltage of the semiconductor substrate region in which the n-channel FET is fabricated. This leads to unwanted high current conditions, and possibly to a well-known positive feedback condition known as CMOS latchup, which can only be interrupted by de-powering of the integrated circuit.
Conventional design techniques avoid turning on the n-channel FET source-to-substrate pn junction diode by fabricating the n-channel FETs in a p-well region of the semiconductor substrate that can be held at the same voltage as the source region of the n-channel FET. This prevents diode turn-on by ensuring that substantially no voltage difference exists between source and substrate regions of the n-channel FET. However, formation of p-well region adds complexity and cost to the fabrication process. A standard single well complementary metal-oxide-semiconductor (CMOS) process typically provides a single well type, which is typically an n-well region in which p-channel FETs are fabricated. Forming the p-well region adds additional masking, ion-implantation, and thermal processing steps to the standard n-well CMOS process, which increases the cost of producing the integrated circuit.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art of integrated circuits and flash memories to provide switching of extreme negative voltages that is compatible with an inexpensive n-well CMOS process, rather than requiring a more expensive twin-well or triple-well (i.e., well-in-well) process.